The present invention relates to a parallel-to-serial converter, and more particularly, to a parallel-to-serial converter for converting parallel data into serial data using a plurality of different clock signals.
FIG. 1 is a circuit diagram of a conventional 4:1 parallel-to-serial converter.
Referring to FIG. 1, the conventional 4:1 parallel-to-serial converter includes flip-flops 101, 103, 105 and 107 and pass gates 109, 111, 113 and 115. The flip-flops 101, 103, 105 and 107 respectively output data DATA0, DATA1, DATA2 and DATA3 in synchronization with rising edges of four clock signals ICLKB, QCLKB, ICLK and QCLK having different phases and lower frequencies than a clock signal CLK. The pass gates 109, 111, 113 and 115 respectively select output signals of the flip-flops 101, 103, 105 and 107 during activation periods of selection clock signals CLKP0/CLKP0B, CLKP1/CLKP1B, CLKP2/CLKP2B and CLKP3/CLKP3B generated by combination of the four clock signals ICLKB, QCLKB, ICLK and QCLK having different phases.
The flip-flops 101, 103, 105 and 107 function to ensure a margin when the pass gates 109, 111, 113 and 115 select the output signals D0, D1, D2 and D3 of the flip-flops 101, 103, 105 and 107.
The selection clock signals CLKP0/CLKP0B, CLKP1/CLKP1B, CLKP2/CLKP2B and CLKP3/CLKP3B allow the pass gates 109, 111, 113 and 115 to select data without overlap when the parallel-to-serial converter serially outputs the parallel data DATA0, DATA1, DATA2 and DATA3. That is, the selection clock signals are made in a pulse form having a suitably adjusted pulse width of the output data.
The clock signals ICLK and QCLKB, the clock signals QCLK and ICLK, the clock signals ICLKB and QCLK, and the clock signals QCLKB and ICLKB are respectively input to NAND gates and inverters to output the selection clock signals CLKP0/CLKP0B, CLKP1/CLKP1B, CLKP2/CLKP2B and CLKP3/CLKP3B. The four clock signals ICLK, ICLKB, QCLK and QCLKB having the different phases are clock signals having a 90-degree phase difference.
Due to the 90-degree phase difference, the clock signals each passing through the NAND gate and the inverter are processed into the pulse-type selection clock signals CLKP0, CLKP1, CLKP2 and CLKP3 having a high level at a portion where high level periods overlap each other.
The clock signals ICLK, ICLKB, QCLK and QCLKB used herein are combined such that the data DATA0, DATA1, DATA2 and DATA3 are output without overlap. The selection clock signals CLKP0/CLKP0B, CLKP1/CLKP1B, CLKP2/CLKP2B and CLKP3/CLKP3B have a pulse form whose high level period is an enable period. Other combinations except the combination of FIG. 1 are also possible.
FIG. 2 is a timing diagram of the conventional 4:1 parallel-to-serial converter illustrated in FIG. 1.
Referring to FIG. 2, the selection clock signals CLKP0/CLKP0B, CLKP1/CLKP1B, CLKP2/CLKP2B and CLKP3/CLKP3B are made in a pulse form by combining the four clock signals ICLK, ICLKB, QCLK and QCLKB having the different phases. At this point, the enable periods of the selection clock signals CLKP0/CLKP0B, CLKP1/CLKP1B, CLKP2/CLKP2B and CLKP3/CLKP3B are not overlapped so that the output data A0, B0, C0 and D0 are output according to their data widths without overlap.
In this case, the selection clock signals CLKP0/CLKP0B, CLKP1/CLKP1B, CLKP2/CLKP2B and CLKP3/CLKP3B have a pulse width narrower than the high or low level periods of the four clock signals ICLK, ICLKB, QCLK and QCLKB having the different phases. That is, assuming that the enable periods of the four clock signals ICLK, ICLKB, QCLK and QCLKB having the different phases are the high or low level periods, it can be seen that the widths of the enable periods of the selection clock signals CLKP0/CLKP0B, CLKP1/CLKP1B, CLKP2/CLKP2B and CLKP3/CLKP3B become narrower than the enable periods of the four clock signals ICLK, ICLKB, QCLK and QCLKB having the different phases.
The reason why the system uses the low-frequency clock signals having the different phases is that it is difficult to use high-frequency clock signals because their high or low level periods have narrow widths and thus their swings are difficult. According to the related art, the four clock signals ICLK, ICLKB, QCLK and QCLKB having the different phases are processed into the pulse-type selection clock signals CLKP0/CLKP0B, CLKP1/CLKP1B, CLKP2/CLKP2B and CLKP3/CLKP3B whose enable periods are narrower than the four clock signals ICLK, ICLKB, QCLK and QCLKB. Therefore, the advantages that can be obtained when the low-frequency clock signals having the different phases may be diluted.
In addition, since the four clock signals ICLK, ICLKB, QCLK and QCLKB having the different phases are processed into a pulse form, the widths of their high or low level periods are reduced. Therefore, there is a limitation in swing for the selection clock signals CLKP0/CLKP0B, CLKP1/CLKP1B, CLKP2/CLKP2B and CLKP3/CLKP3B. The duty ratio may be varied. Therefore, the pass gates 109, 111, 113 and 115 may not exactly select the data D0, D1, D2 and D3.
Furthermore, since the data D0, D1, D2 and D3 are selected using the pass gates 109, 111, 113 and 115, the swing widths of the output data A0, B0, C0 and D0 may be restricted by junction capacitances of the pass gates 109, 111, 113 and 115 and jitters may also be caused.